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| publication number 22143 revision c amendment 7 issue date may 9, 2006 am29pl160c data sheet retired product this product has been retired and is not recomme nded for designs. for new designs, s29gl016a supersedes am29pl160c. please refer to the s 29gl-a family data sheet for specifications and ordering information. availability of this document is retained for referenc e and historical purposes only. the following document contains inform ation on spansion memory products. continuity of specifications there is no change to this data sheet as a result of offering the device as a spansion product. any changes that have been made are the result of no rmal data sheet improvement and are noted in the document revision summary. for more information please contact your local sales office for additi onal information about spansion memory solutions.
this page left intentionally blank. data sheet this data sheet states amd?s current specifications regar ding the products described herein. this data sheet may be revised by subsequent versions or modificati ons due to changes in technical specifications. publication# 22143 rev: c amendment: 7 issue date: may 9, 2006 am29pl160c 16 megabit (2 m x 8-bit/1 m x 16-bit) cmos 3.0 volt-only high performance page mode flash memory distinctive characteristics 16 mbit page mode device ? byte (8-bit) or word (16-bit) mode selectable via byte# pin ? page size of 16 bytes/8 words: fast page read access from random locations within the page single power supply operation ? full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications ? regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors 5 v-tolerant data, address, and control signals high performance read access times ? page access times as fast as 25 ns at industrial temperature range ? random access times as fast as 65 ns power consumption (typical values at 5 mhz) ? 30 ma read current ? 20 ma program/erase current ? 1 a standby mode current ? 1 a automatic sleep mode current flexible sector architecture ? sector sizes: one 16 kbyte, two 8 kbyte, one 224 kbyte, and seven sectors of 256 kbytes each ? supports full chip erase bottom boot block configuration only sector protection ? a hardware method of locking a sector to prevent any program or erase operations within that sector ? sectors can be locked via programming equipment ? temporary sector unprotect command sequence allows code changes in previously locked sectors minimum 1 million write cycles guarantee per sector 20-year data retention manufactured on 0.32 m process technology software command-set compatible with jedec standard ? backward compatible with am29f and am29lv families cfi (common flash interface) compliant ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences erase suspend/erase resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation package options ? 44-pin so (mask-rom compatible pinout) ? 48-pin tsop this product has been retired and is not recommended for designs. for new designs, s29gl016a supersedes am29pl160c. please refe r to the s29gl-a family data sheet for specifica- tions and ordering information. availability of this document is retained for reference and historical purposes only. 2 am29pl160c 22143c7 may 9, 2006 data sheet general description the am29pl160c is a 16 mbit, 3.0 volt-only page mode flash memory device organized as 2,097,152 bytes or 1,048,576 words.the device is offered in a 44- pin so or a 48-pin tsop package. the word-wide data (x16) appears on dq15?dq0; the byte-wide (x8) data appears on dq7?dq0. this device can be pro- grammed in-system or with in standard eprom programmers. a 12.0 v v pp or 5.0 v cc are not required for write or erase operations. the device offers access times of 65, 70, and 90 ns, al- lowing high speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable (ce#), write enable (we#), and output enable (oe#) controls. the sector sizes are as follows: one 16 kbyte, two 8 kbyte, one 224 kbyte and seven sectors of 256 kbytes each. the device is available in both top and bottom boot versions. page mode features the device is ac timing, pinout, and package compat- ible with 16 mbit x 16 page mode mask rom . the page size is 8 words or 16 bytes. after initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. standard flash memory features the device requires only a single 3.0 volt power sup- ply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the command register using standard microprocessor write timings. register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. write cy- cles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm?an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase com- mand sequence. this initiates the embedded erase algorithm?an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both these modes. amd?s flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection. may 9, 2006 22143c7 am29pl160c 3 data sheet table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . 7 device bus operations . . . . . . . . . . . . . . . . . . . . . . 8 table 1. am29pl160c device bus operations ................................8 word/byte configuration .......................................................... 8 requirements for reading array data ..................................... 8 read mode ............................................................................... 8 random read (non-page mode read) ............................................8 page mode read ...................................................................... 9 table 2. word mode ..........................................................................9 table 3. byte mode ...........................................................................9 writing commands/command sequences ............................ 10 program and erase operation status .................................... 10 standby mode ........................................................................ 10 automatic sleep mode ........................................................... 10 output disable mode .............................................................. 10 table 4. sector address table, bottom boot (am29pl160cb) ......11 autoselect mode ..................................................................... 12 table 5. am29pl160c autoselect codes (high voltage method) ..12 sector protection/unprotection ............................................... 12 common flash memory interface (cfi) . . . . . . . 13 table 6. cfi query identification string ..........................................13 table 7. system interface string .....................................................14 table 8. device geometry definition ..............................................14 table 9. primary vendor-specific extended query ........................15 hardware data protection . . . . . . . . . . . . . . . . . . 15 low v cc write inhibit ......................................................................15 write pulse ?glitch? protection ........................................................15 logical inhibit ..................................................................................15 power-up write inhibit ....................................................................15 command definitions . . . . . . . . . . . . . . . . . . . . . . 16 reading array data ................................................................ 16 reset command ..................................................................... 16 autoselect command sequence ............................................ 16 word/byte program command sequence ............................. 16 unlock bypass command sequence ..............................................17 figure 1. program operation .......................................................... 17 chip erase command sequence ........................................... 17 sector erase command sequence ........................................ 18 erase suspend/erase resume commands ........................... 18 temporary unprotect enable/disable command sequence .. 19 figure 2. erase operation............................................................... 19 command definitions ............................................................. 20 table 10. am29pl160c command definitions ..............................20 write operation status . . . . . . . . . . . . . . . . . . . . 21 dq7: data# polling ................................................................. 21 figure 3. data# polling algorithm ................................................... 21 dq6: toggle bit ...................................................................... 22 dq2: toggle bit ...................................................................... 22 reading toggle bits dq6/dq2 .............................................. 22 dq5: exceeded timing limits ................................................ 22 figure 4. toggle bit algorithm........................................................ 23 dq3: sector erase timer ....................................................... 23 table 11. write operation status ................................................... 24 absolute maximum ratings. . . . . . . . . . . . . . . . . 25 figure 5. maximum negative overshoot waveform ...................... 25 figure 6. maximum positive overshoot waveform........................ 25 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . 25 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7. i cc1 current vs. time (showing active and automatic sleep currents) .............................................................................. 27 figure 8. typical i cc1 vs. frequency ............................................. 27 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9. test setup....................................................................... 28 table 12. test specifications ......................................................... 28 key to switching waveforms . . . . . . . . . . . . . . . 28 figure 10. input waveforms and measurement levels ................. 28 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11. conventional read operations timings ....................... 30 figure 12. page read timings ...................................................... 30 figure 13. byte# timings for read operations............................ 31 figure 14. byte# timings for write operations............................ 31 figure 15. program operation timings.......................................... 33 figure 16. ac waveforms for chip/sector erase operations........ 34 figure 17. data# polling timings (during embedded algorithms). 34 figure 18. toggle bit timings (during embedded algorithms)...... 35 figure 19. dq2 vs. dq6 for erase and erase suspend operations ............................................................ 35 figure 20. alternate ce# controlled write operation timings ...... 37 erase and programming performance . . . . . . . 38 latchup characteristics . . . . . . . . . . . . . . . . . . . . 38 tsop and so pin capacitance . . . . . . . . . . . . . . 38 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 39 ts 048?48-pin standard thin small outline package ......... 39 so 044?44-pin small outline package, standard pinout .... 40 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 41 revision a (august 1998) ....................................................... 41 revision a+1 (september 1998) ............................................ 41 revision b (january 1999) ..................................................... 41 revision b+1 (february 1999) ................................................ 41 revision b+2 (march 5, 1999) ................................................ 41 revision b+3 (may 14, 1999) ................................................. 41 revision b+4 (june 25, 1999) ................................................ 41 revision b+5 (july 26, 1999) .................................................. 41 revision b+6 (september 2, 1999) ........................................ 41 revision b+7 (february 4, 2000) ............................................ 41 revision c (february 21, 2000) .............................................. 41 revision c+1 (june 20, 2000) ................................................ 41 revision c+2 (june 28, 2000) ................................................ 41 revision c+3 (november 14, 2000) ....................................... 41 revision c+4 (june 12, 2002) ................................................ 41 revision c+5 (june 10, 2004) ................................................ 41 revision c+6 (february 16, 2006) ......................................... 41 revision c7 (may 9, 2006) ..................................................... 42 4 am29pl160c 22143c7 may 9, 2006 data sheet product selector guide note: see ?ac characteristics? for full specifications. block diagram family part number am29pl160c speed option regulated voltage range: v cc =3.0?3.6 v -65r -70r full voltage range: v cc = 2.7?3.6 v -90 max access time, ns (t acc )657090 max ce# access time, ns (t ce )657090 max page access time, ns (t pac c )252530 max oe# access time, ns (t oe )252530 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# byte# ce# oe# stb stb dq0 ? dq15 data latch y-gating cell matrix address latch a0?a19 a-1 may 9, 2006 22143c7 am29pl160c 5 data sheet connection diagrams ce# byte# a7 a16 a15 a14 a13 a12 a11 a10 a9 a8 a19 we# nc a18 a17 a6 a5 a4 a3 a2 a1 a0 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 nc dq10 v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq2 dq9 dq1 dq8 dq0 oe# v ss nc dq12 dq4 v cc v cc v ss dq11 dq3 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 48-pin standard tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 we# a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce# v ss oe# dq0 dq8 dq1 dq9 dq2 dq10 dq3 dq11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc 44-pin standard so 6 am29pl160c 22143c7 may 9, 2006 data sheet pin configuration a0?a19 = 20 address inputs dq0?dq15 = 16 data inputs/outputs dq15/a-1 = in word mode, functions as dq15 (msb data input/output) in byte mode, functions as a-1 (lsb address input) byte# = byte enable input when low, enables byte mode when high, enables word mode ce# = chip enable input oe# = output enable input we# = write enable input v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 20 16 or 8 dq0?dq15 (a-1) a0?a19 ce# oe# we# byte# may 9, 2006 22143c7 am29pl160c 7 data sheet ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combi- nation) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. am29pl160c b -65r s i temperature range i = industrial (?40 c to +85 c) f = industrial (?40 c to +85 c) with pb-free package package type e = 48-pin standard thin small outline package (ts 048) (bottom boot devices only) s = 44-pin small outline package, standard pinout (so 044) speed option see product selector guide and valid combinations boot code sector architecture b= bottom sector device number/description am29pl160c 16 megabit (1 m x 16-bit) cmos 3.0 volt-only high performance page mode flash memory valid combinations (bottom boot) voltage range am29pl160cb-65r ei, si, ef, sf v cc = 3.0?3.6 v am29pl160cb-70r am29pl160cb-90 v cc = 2.7?3.6 v 8 am29pl160c 22143c7 may 9, 2006 data sheet device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register it- self does not occupy any addressable memory location. the register is composed of latches that store the commands, along with the address and data infor- mation needed to execute the command. the contents of the register serve as inputs to the internal state ma- chine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the re- sulting output. the following subsections describe each of these operations in further detail. table 1. am29pl160c device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5 v, x = don?t care, a in = address in, d in = data in, d out = data out notes: 1. addresses are a19:a0 in word mode (byte# = v ih ), a19:a-1 in byte mode (byte# = v il ). 2. the sector protect and sector unprotect functions must be implemented via programming equipment. see the ?sector protection/unprotection? section. word/byte configuration the byte# pin controls whether the device data i/o pins dq15?dq0 operate in the byte or word configura- tion. if the byte# pin is set at logic ?1?, the device is in word configuration, dq15?dq0 are active and con- trolled by ce# and oe#. if the byte# pin is set at logi c ?0?, the device is in byte configuration, and only data i/o pins dq0?dq7 are active and controlled by ce# and oe#. the data i/o pins dq8?dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should re- main at v ih . the byte# pin determines whether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a reset command (when not executing a program or erase operation). this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read operations table for timing specifica- tions and to figure 11 for the timing diagram. i cc1 in the dc characteristics table represents the active cur- rent specification for reading array data. read mode random read (non-page mode read) the device has two control functions which must be satisfied in order to obtain data at the outputs. ce# is the power control and should be used for device selec- tion. oe# is the output control and should be used to gate data to the output pins if the device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ad- dresses and stable ce# to valid data at the output pins. the output enable access time is the delay from the falling edge of oe# to valid data at the output pins (assuming the addresses have been stable for at least t acc ?t oe time). operation ce# oe# we# addresses (note 1) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h a in d out d out dq8?dq14 = high-z, dq15 = a-1 write l h l a in d in d in standby v cc 0.3 v x x x high-z high-z high-z output disable l h h x high-z high-z high-z may 9, 2006 22143c7 am29pl160c 9 data sheet page mode read the am29pl160c is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the am29pl160c device is 8 words, or 16 bytes, with the appropriate page being selected by the higher address bits a3?a19 and the lsb bits a0?a2 (in the word mode) and a-1 to a2 (in the byte mode) determining the specific word/byte within that page. this is an asynchronous operation with the micropro- cessor supplyin g the specific word or byte location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pac c . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . here again, ce# selects the device and oe# is the output control and should be used to gate data to the output pins if the device is se- lected. fast page mode accesses are obtained by keeping a3?a19 constant and changing a0 to a2 to select the specific word, or changing a-1 to a2 to se- lect the specific byte, within that page. the following tables determine the specific word and byte within the selected page: table 2. word mode table 3. byte mode word a2 a1 a0 word 0 000 word 1 001 word 2 010 word 3 011 word 4 100 word 5 101 word 6 110 word 7 111 byte a2 a1 a0 a-1 byte 0 0 0 0 0 byte 1 0 0 0 1 byte 2 0 0 1 0 byte 3 0 0 1 1 byte 4 0 1 0 0 byte 5 0 1 0 1 byte 6 0 1 1 0 byte 7 0 1 1 1 byte 8 1 0 0 0 byte 9 1 0 0 1 byte 10 1 0 1 0 byte 11 1 0 1 1 byte 12 1 1 0 0 byte 13 1 1 0 1 byte 14 1 1 1 0 byte 15 1 1 1 1 10 am29pl160c 22143c7 may 9, 2006 data sheet writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whether the device accepts program data in bytes or words. refer to ?word/byte configuration? for more information. the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a word or byte, instead of four. the ?word/byte program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 4 indicates the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. the ?command definitions? section has de- tails on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? and ?autoselect command sequence? sections for more information. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the ?ac characteristics? section c ontains timing specification tables and timing diagrams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on dq7?dq0. standard read cycle timings and i cc read specifications apply. refer to ?write operation status? for more information, and to ?ac characteris- tics? for timing diagrams. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# pin is both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# is held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for tacc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. note that during automatic sleep mode, oe# must be at vih before the device reduces current to the stated sleep mode specification. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high imped- ance state. may 9, 2006 22143c7 am29pl160c 11 data sheet table 4. sector address table, bottom boot (am29pl160cb) sector a19 a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) address range (in hexadecimal) byte mode (x8) word mode (x16) sa0 0000000x 16/8 00 0000?003fff 00000?01fff sa1 00000010 8/4 00 4000?005fff 02000?02fff sa2 00000011 8/4 00 6000?007fff 03000?03fff sa3 0 0 0 01000?11111 224/112 008000?03ffff 04000?1ffff sa4 0 0 1xxxxx 256/128 040000 ?07ffff 20000?3ffff sa5 0 1 0xxxxx 256/128 080000?0bffff 40000?5ffff sa6 0 1 1xxxxx 256/128 0c000 0?0fffff 60000?7ffff sa7 1 0 0xxxxx 256/128 100000 ?13ffff 80000?9ffff sa8 1 0 1xxxxx 256/128 140000 ?17ffff a0000?bffff sa9 1 1 0xxxxx 256/128 180000?1bffff c0000?dffff sa101 1 1xxxxx 256/128 1c000 0?1fffff e0000?fffff 12 am29pl160c 22143c7 may 9, 2006 data sheet autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. how- ever, the autoselect codes can also be accessed in- system through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in table 5. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (table 4). table 5 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the pro- gramming equipment may then read the corresponding identifier code on dq7-dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 10. this method does not require v id . see ?command definitions? for details on using the autoselect mode. table 5. am29pl160c autoselect codes (high voltage method) l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. note: the autoselect codes may also be accessed in-system via command sequences. see table 10. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is protected or unprotected. see ?autoselect mode? for details. sector protection and unprotection must be imple- mented using programming equipment. the procedure requires v id on address pin a9 and oe#. details on this method are provided in a supplement, publication number 22239. contact an amd representative to re- quest a copy. the device features a temporary unprotect command sequence to allow changing array data in-system. see ?temporary unprotect enable/disable command se- quence? for more information. description mode ce# oe# we# a19 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id : amd l l h x x v id xlxll x 01h device id: am29pl160c (bottom boot block) word l l h xxv id xlxlh 22h 45h byte l l h x 45h sector protection verification l l h sa x v id xlxhl x 01h (protected) x 00h (unprotected) may 9, 2006 22143c7 am29pl160c 13 data sheet common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host syst em software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of de- vices. software support can then be device- independent, jedec id-independent, and forward- and backward-compatible for the specified flash de- vice families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cf i query mode when the sys- tem writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in ta- bles 6?9. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode , and the system can read cfi data at the addresses given in tables 6?9. the system must write the reset command to return the de- vice to the autoselect mode. for further information, plea se refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/products/nvd/over- view/cfi.html. alternatively, contact an amd representative for copies of these documents. table 6. cfi query identification string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) 14 am29pl160c 22143c7 may 9, 2006 data sheet table 7. system interface string addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase), d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0004h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) table 8. device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0015h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 58h 0004h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0000h 0000h 0040h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 0001h 0000h 0020h 0000h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0080h 0003h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0006h 0000h 0000h 0004h erase block region 4 information may 9, 2006 22143c7 am29pl160c 15 data sheet hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 10 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must pro- vide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to reading array data on power-up. table 9. primary vendor-specific extended query addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0030h minor version number, ascii 45h 8ah 0000h address sensitive unlock 0 = required, 1 = not required 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 01 = 29f040 mode, 02 = 29f016 mode, 03 = 29f400 mode, 04 = 29lv800a mode 4ah 94h 0000h simultaneous operation 00 = not supported, 01 = supported 4bh 96h 0000h burst mode type 00 = not supported, 01 = 4 word linear burst, 02 = 8 word linear burst, 03 = 32 linear burst, 04 = 4 word interleave burst 4ch 98h 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 16 am29pl160c 22143c7 may 9, 2006 data sheet command definitions writing specific address and data commands or se- quences into the command register initiates device operations. table 10 defines the valid register com- mand sequences. writing incorrect address and data values or writing them in the improper se- quence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate timing diagrams in the ?ac characteristics? section. reading array data the device is automaticall y set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or em- bedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the sys- tem can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more infor- mation on this mode. the system must issue the reset command to re-en- able the device for reading array data if dq5 goes high, or while in the autoselect mode. see the ?reset command? section, next. see also ?requirements for reading array data? in the ?device bus operations? section for more information. the read operations table provides the read parame- ters, and figure 11 shows the timing diagram. reset command writing the reset command to the device resets the de- vice to reading array data. address bits are don?t care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manu facturer and devices codes, and determine whether or not a sector is protected. table 10 shows the address and data requirements. this method is an alternative to that shown in table 5, which is intended for prom programmers and re- quires v id on address bit a9. the autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufacturer code. a read cycle at address xx01h re- turns the device code. a read cycle containing a sector address (sa) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is pro- tected, or 00h if it is unprotected. refer to table 4 for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. word/byte program command sequence the system may program the device by word or byte, depending on the state of the byte# pin. program- ming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. the program address and data are written next, which in turn initiate the embedded program algo- rithm. the system is not required to provide further controls or timings. the device automatically gener- ates the program pulses and verifies the programmed cell margin. table 10 shows the address and data re- quirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. see ?write operation status? for informa- tion on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. may 9, 2006 22143c7 am29pl160c 17 data sheet programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may halt the operation and set dq5 to ?1,? or cause the data# polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1?. unlock bypass command sequence the unlock bypass feature allows the system to pro- gram bytes or words to the device faster than using the standard program command sequence. the unlock by- pass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the de- vice then enters the unlo ck bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the pro- gram address and data. additional data is programmed in the same manner. this mode dis- penses with the initial two unl ock cycles required in the standard program command sequence, resulting in faster total programming time. table 10 shows the re- quirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don?t care for both cycles. the device then returns to reading array data. figure 1 illustrates the algor ithm for the program oper- ation. see the program/erase operations table in ?ac characteristics? for parameters, and to figure 15 for timing diagrams. note: see table 10 for program command sequence. figure 1. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 10 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embed- ded erase algorithm are ignored. the system can determine the status of the erase op- eration by using dq7, dq6, or dq2. see ?write operation status? for inform ation on these status bits. when the embedded erase algorithm is complete, the start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress 18 am29pl160c 22143c7 may 9, 2006 data sheet device returns to reading array data and addresses are no longer latched. figure 2 illustrates the algorithm for the erase opera- tion. see the program/erase operations tables in ?ac characteristics? for parameters, and to figure 16 for timing diagrams. sector erase co mmand sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. table 10 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. the in- terrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sect or erase or erase sus- pend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector ad- dresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the ?dq3: sector erase timer? section.) the time-out begins from the rising edge of the final we# pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the sta- tus of the erase operation by using dq7, dq6, or dq2. (refer to ?write operation status? for information on these status bits.) figure 2 illustrates the algorithm for the erase opera- tion. refer to the program/erase operations tables in the ?ac characteristics? section for parameters, and to figure 16 for timing diagrams. erase suspend/erase resume commands the erase suspend command allows the system to in- terrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algo- rithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. ad- dresses are ?don?t-cares? when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maxi- mum of 20 s to suspend the erase operation. however, when the erase suspend command is writ- ten during the sector erase time-out, the device immediately terminates the time-out period and sus- pends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors sele cted for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sec- tors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see ?write operation status? for information on these status bits. after an erase-suspended program operation is com- plete, the system can once again read array data within non-suspended sectors. the system can deter- mine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see ?autoselect command sequence? for more information. the system must write the erase resume command (address bits are ?don?t care?) to exit the erase sus- may 9, 2006 22143c7 am29pl160c 19 data sheet pend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. temporary unprotect enable/disable command sequence the temporary unprotect command sequence is a four-bus-cycle operation. the sequence is initiated by writing two unlock write cycles. a third write cycle sets up the command. the fourth and final write cycle en- ables or disables the temporary unprotect feature. if the temporary unprotect feature is enabled, all sectors are temporarily unprotected. the system may program or erase data as needed. when the system writes the temporary unprotect disable command sequence, all sectors return to their previous protected or unpro- tected settings. see table 10 for more information. notes: 1. see table 10 for erase command sequence. 2. see ?dq3: sector erase timer? for more information. figure 2. erase operation start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress 20 am29pl160c 22143c7 may 9, 2006 data sheet command definitions table 10. am29pl160c command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a19?a12 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and t he fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t cares for unlock and command cycles. 5. address bits a19?a11 are don?t cares for unlock and command cycles, unless sa or pa required. 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 8. the fourth cycle of the autoselect command sequence is a read cycle. 9. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more information. 10. command is valid when device is ready to read array data or when device is in autoselect mode. 11. the unlock bypass command is required prior to the unlock bypass program command. 12. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 13. the system may read and progra m in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 14. the erase resume command is valid only during the erase sus- pend mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 555 90 x00 01 byte aaa 555 aaa device id, bottom boot block word 4 555 aa 2aa 55 555 90 x01 2245 byte aaa 555 aaa x02 45 sector protect verify (note 9) word 4 555 aa 2aa 55 555 90 (sa) x02 xx00 xx01 byte aaa 555 aaa (sa) x04 00 01 cfi query (note 10) word 1 55 98 byte aa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 11) 2 xxx a0 pa pd unlock bypass reset (note 12) 2 xxx 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 13) 1 xxx b0 erase resume (note 14) 1 xxx 30 temporary unprotect enable word 4 555 aa 2aa 55 555 e0 xxx 01 byte aaa 555 aaa temporary unprotect disable word 4 555 aa 2aa 55 555 e0 xxx 00 byte aaa 555 aaa may 9, 2006 22143c7 am29pl160c 21 data sheet write operation status the device provides several bits to determine the sta- tus of a write operation: dq2, dq3, dq5, dq6, and dq7. table 11 and the following subsections describe the functions of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase com- mand sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to programming during erase suspend. when the em- bedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pr ogram address falls within a protected sector, data# polling on dq7 is active for ap- proximately 1 s, then the device returns to reading array data. during the embedded eras e algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. this is analogous to the complement/true datum out- put described for the embedded program algorithm: the erase function changes all the bits in a sector to ?1?; prior to this, the device outputs the ?complement,? or ?0.? the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the de- vice returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7?dq0 on the following read cycles. this is be- cause dq7 may change asynchronously with dq0? dq6 while output enable (o e#) is asserted low. see figure 16 in the ?ac ch aracteristics? section. table 11 shows the outputs for data# polling on dq7. figure 3 shows the data# polling algorithm. notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-pr otected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5 figure 3. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start 22 am29pl160c 22143c7 may 9, 2006 data sheet dq6: toggle bit toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase op- eration), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycl es.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro- tected sectors, and ignore s the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on ?dq7: data# polling?). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 11 shows the outputs for toggle bit i on dq6. figure 4 shows the toggle bit algorithm in flowchart form, and the section ?reading toggle bits dq6/dq2? explains the algorithm. figure 18 in the ?ac character- istics? section shows the toggle bit timing diagrams. figure 19 shows the differences between dq2 and dq6 in graphical form. see also the subsection on ?dq2: toggle bit?. dq2: toggle bit the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the syst em reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 11 to compare outputs for dq2 and dq6. figure 4 shows the toggle bit algorithm in flowchart form, and the section ?reading toggle bits dq6/dq2? explains the algorithm. see also the dq6: toggle bit subsection. figure 18 shows the toggle bit timing dia- gram. figure 19 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 4 for the following discussion. when- ever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initia l two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 4). dq5: exceeded ti ming limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure may 9, 2006 22143c7 am29pl160c 23 data sheet condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a ?1.? under both these conditions , the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if addi- tional sectors are selected for erasure, the entire time- out also applies after each additional sector erase command. when the time-out is complete, dq3 switches from ?0? to ?1.? the system may ignore dq3 if the system can guarantee that the time between addi- tional sector erase command s will always be less than 50 s. see also the ?write operation status? section. after the sector erase command sequence is written, the system should read the status on dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure the device has accepted the command sequence, and then read dq3. if dq3 is ?1?, the internally controlled erase cycle has begun; all further commands (other than erase suspend) are ignored until the erase operation is com- plete. if dq3 is ?0?, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 11 shows the outputs for dq3. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to ?1?. see text. figure 4. toggle bit algorithm (note 1) (notes 1, 2) 24 am29pl160c 22143c7 may 9, 2006 data sheet table 11. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedde d erase operation has exceeded the maximum timing limits. see ?dq5: exceeded timing limits? for more information. 2. dq7 and dq2 require a valid address when reading status inform ation. refer to the appropriate subsection for further details. operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle embedded erase algorithm 0 toggle 0 1 toggle erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle reading within non-erase suspended sector data data data data data erase-suspend-program dq7# toggle 0 n/a n/a may 9, 2006 22143c7 am29pl160c 25 data sheet absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . -65c to +150c ambient temperature with power applied. . . . . . . . . . . . . . -65c to +125c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9 and oe# (note 2) . . . . . . . . . .?0.5 v to +13.0 v all other pins (note 1). . . . . . . . . . . ?0.5 v to +5.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input at i/o pins may overshoot v ss to -2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions output pins may overshoot to v cc + 2.0 v for periods up to 20 ns. 2. minimum dc input voltage on pins a9 and oe# is ?0.5 v. during voltage transitions, a9 and oe# may overshoot v ss to -2.0 v for periods of up to 20 ns. maximum dc input voltage on pin a9 and oe# is +13.0 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short ci rcuit should not be greater than one second. 4. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the de- vice at these or any other conditions above those indi- cated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rat- ing conditions for extended periods may affect device re- liability. operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . . 0c to +70c industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c v cc supply voltages v cc for regulated voltage range. . . . . . . 3.0 v to 3.6 v v cc for full voltage range . . . . . . . . . . . . 2.7 v to 3.6 v operating ranges define those li mits between which the func- tionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 5. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 6. maximum positive overshoot waveform 26 am29pl160c 22143c7 may 9, 2006 data sheet dc characteristics cmos compatible notes: 1. the i cc current listed is typically le ss than 2 ma/mhz, with oe# at v ih . typical v cc is 3.0 v. 2. maximum i cc specifications are tested with v cc = v cc max. 3. the automatic sleep mode current is dependent on the state of oe#. 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 6. not 100% tested. parameter symbol description test conditions min typ max unit i li input load current v in = v ss to 5.5 v, v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to 5.5 v, v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1, 2) ce# = v il, oe# = v ih 30 50 ma i cc2 v cc active write current (notes 2, 4, 5) ce# = v il, oe# = v ih 20 30 ma i cc3 v cc standby current (note 2) ce# = v cc 0.3 v 1 5 a i cc4 automatic sleep mode (notes 2, 3, 6) v ih = v cc 0.3 v; v il = v ss 0.3 v oe# = v ih 15 a oe# = v il 820 v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 x v cc 5.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.3 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min 0.85 x v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage (note 4) 2.3 2.5 v may 9, 2006 22143c7 am29pl160c 27 data sheet dc characteristics (continued) zero power flash note: addresses are switching at 1 mhz figure 7. i cc1 current vs. time (showing active and automatic sleep currents) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 12345 frequency in mhz supply current in ma note: t = 25 c figure 8. typical i cc1 vs. frequency 2.7 v 3.6 v 4 6 28 am29pl160c 22143c7 may 9, 2006 data sheet test conditions table 12. test specifications key to switching waveforms 2.7 k c l 6.2 k 3.3 v device under te s t figure 9. test setup note: diodes are in3064 or equivalent test condition -65r -70r, -90 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input figure 10. input waveforms and measurement levels may 9, 2006 22143c7 am29pl160c 29 data sheet ac characteristics read operations notes: 1. not 100% tested. 2. see figure 9 and table 12 for test specifications. parameter description test setup speed options unit jedec std -65r -70r -90 t avav t rc read cycle time min 65 70 90 ns t avqv t acc address access time ce#=v il , oe#=v il max 65 70 90 ns t elqv t ce chip enable to output delay oe#=v il max 65 70 90 ns t pac c page access time max 25 25 30 ns t glqv t oe output enable to output valid max 25 25 30 ns t ehqz t df chip enable to output high z max 20 ns t ghqz t df output enable to output high z max 20 ns t oeh output enable hold time (note 1) read 0 ns toggle and data# polling 10 ns t axqx t oh output hold time from addresses min 0 ns 30 am29pl160c 22143c7 may 9, 2006 data sheet ac characteristics figure 11. conventional read operations timings note: word configuration: toggle a0, a1, a2. byte configuration: toggle a-1, a0, a1, a2. figure 12. page read timings t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v t df t oh a3 - a19 ce# oe# a - 1 - a2 data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c may 9, 2006 22143c7 am29pl160c 31 data sheet ac characteristics word/byte configuration (byte#) parameter description speed options unit jedec std -65r -70r -90 t elfl/ t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high z max 25 25 30 ns t fhqv byte# switching high to ou tput active min657090ns dq15 output data output (dq0?dq7) ce# oe# byte# t elfl dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t flqz byte# switching from word to byte mode dq15 output data output (dq0?dq7) byte# t elfh dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t fhqv byte# switching from byte to word mode figure 13. byte# timings for read operations note: refer to the erase/program operations table for t as and t ah specifications. figure 14. byte# timings for write operations ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as ) 32 am29pl160c 22143c7 may 9, 2006 data sheet ac characteristics program/erase operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter description speed options unit jedec std -65r -70r -90 t avav t wc write cycle time (note 1) min 65 70 90 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 45 45 45 ns t dvwh t ds data setup time min 35 35 45 ns t whdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 35 35 ns t whwl t wph write pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) byte typ 7 s word typ 9 t whwh2 t whwh2 sector erase operation (note 2) typ 5 sec t vcs v cc setup time (note 1) min 50 s may 9, 2006 22143c7 am29pl160c 33 data sheet ac characteristics notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode. figure 15. program operation timings oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t ghwl t cs status d out program command sequence (last two cycles) t ch pa 34 am29pl160c 22143c7 may 9, 2006 data sheet ac characteristics notes: 1. sa = sector address (for sector erase), va = valid addr ess for reading status data (see ?write operation status?). 2. illustration shows device in word mode. figure 16. ac waveforms for chip/sector erase operations note: va = valid address. illustration shows first status cycle after command sequence, last st atus read cycle, and array data read cycle figure 17. data# polling timings (during embedded algorithms) oe# ce# addresses v cc we# data 2aah sa t ghwl t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data we# ce# oe# high z t oe high z dq7 dq0?dq6 complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc may 9, 2006 22143c7 am29pl160c 35 data sheet ac characteristics note: va = valid address; not required for dq6. illustration shows first two status cycle af ter command sequence, last status read cycle, and array data read cycle figure 18. toggle bit timings (during embedded algorithms) we# ce# oe# high z t oe dq6/dq2 addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va note: the system may use ce# or oe# to toggle dq2 and dq 6. dq2 toggles only when read at an address within an erase-suspended sector. figure 19. dq2 vs. dq6 for erase and erase suspend operations enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing 36 am29pl160c 22143c7 may 9, 2006 data sheet ac characteristics alternate ce# cont rolled erase/pr ogram operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter description speed options unit jedec std -65r -70r -90 t avav t wc write cycle time (note 1) min 65 70 90 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 45 45 ns t dveh t ds data setup time min 35 35 45 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 35 35 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) byte typ 7 s word typ 9 t whwh2 t whwh2 sector erase operation (note 2) typ 5 sec may 9, 2006 22143c7 am29pl160c 37 data sheet ac characteristics notes: 1. pa = program address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 2. figure indicates the last two bus cycles of the command sequence. 3. word mode address used as an example. t ghel t ws oe# ce# we# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t whwh1 or 2 t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase figure 20. alternate ce# controlled write operation timings 38 am29pl160c 22143c7 may 9, 2006 data sheet erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maxi mum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 10 for further information on command definitions. 6. the device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. latchup characteristics includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. tsop and so pi n capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention * for reference only. bsc is an ansi standard for basic space centering. parameter typ (note 1) max (note 2) unit comments sector erase time 5 60 s excludes 00h programming prior to erasure (note 4) chip erase time 40 s byte programming time 7 300 s excludes system level overhead (note 5) word programming time 9 360 s chip programming time (note 3) byte mode 14 42 s word mode 9 27 s description min max input voltage with respect to v ss on all pins except i/o pins (including a9 and oe#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf so 8 10 pf parameter test conditions min unit minimum pattern data retention time 150 c10 years 125 c20 years may 9, 2006 22143c7 am29pl160c 39 data sheet physical dimensions ts 048?48-pin standard thin small outline package dwg rev aa; 10/99 40 am29pl160c 22143c7 may 9, 2006 data sheet physical dimensions so 044?44-pin smal l outline package, standard pinout dwg rev ac; 10/99 may 9, 2006 22143c7 am29pl160c 41 data sheet revision summary revision a (august 1998) initial release. revision a+1 (september 1998) sector protection/unprotection added reference to temporary unprotect enable/dis- able command sequence. common flash memory interface (cfi) deleted reference to upper address bits in word mode. revision b (january 1999) ordering information deleted commercial temperature rating. dc characteristics corrected i cc1 test condition for oe# to v ih . revision b+1 (february 1999) dc characteristics replaced tbds for i cc4 with specifications. revision b+2 (march 5, 1999) distinctive characteristics in the first subbullet under the flexible sector architec- ture bullet, deleted the reference to ?one 8 kbyte? sector. revision b+3 (may 14, 1999) global deleted the 60r speed option and added the 65r speed option. common flash memory interface (cfi) corrected the data for the following cfi hex addreses: 38, 39, 3c, 4c. absolute maximum ratings corrected the maximum rating for all other pins to +5.5 v. revision b+4 (june 25, 1999) changed data sheet status to preliminary. deleted the 70 ns, full voltage range speed option. revision b+5 (july 26, 1999) global added the reverse pinout so package. deleted the tsop package. physical dimensions restored section. revision b+6 (september 2, 1999) connection diagrams corrected the pinouts of pins 1, 2, 43, and 44 on the reverse so diagram. revision b+7 (febr uary 4, 2000) global added 48-pin tsop. revision c (february 21, 2000) global the ?preliminary? designation has been removed from the document. parameters are now stable, and only speed, package, and temperature range combinations are expected to change in future data sheet revisions. added dash to ordering part numbers. revision c+1 (june 20, 2000) global deleted the sor44 package. deleted references to top boot configuration. product selector guide, ordering information added -90r speed option. revision c+2 (june 28, 2000) command definitions command definitions table: corrected address in the sixth cycle of the chip erase command sequence from 2aa to aaa. revision c+3 (november 14, 2000) added table of contents. revision c+4 (june 12, 2002) global deleted references to hard ware reset (reset#) input. added reverse pinout so package. deleted 90r speed option. tsop and so pin capacitance added tsop pin capacitance. revision c+5 (june 10, 2004) ordering information added pb-free package opns revision c+6 (febr uary 16, 2006) global deleted 120 ns speed option. 42 am29pl160c 22143c7 may 9, 2006 data sheet revision c7 (may 9, 2006) added migration and obsolescence information. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita- tion, ordinary industrial use, general o ffice use, personal use, and household use, but are not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers th at, unless extremely high safety is secured, could have a seri ous effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor de- vices have an inherent chance of failure. y ou must protect against injury, damage or loss from such failures by incorporating s afety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of ov er-current levels and other abn ormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on expor t under the foreign exchange and foreign trade law of japan, the us export administra tion regulations or the applicable laws of any other country, the prior au- thorization by the respective government entit y will be required for export of those products trademarks copyright ? 2004?2006 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are regi stered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies . |
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